File:Riedel-research-mitra-reconfigurable-low-latency-and-power-efficient-in-memory-stochasti-0ccb97f9.jpg

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Revision as of 23:55, 18 August 2026 by MarcRiedel (talk | contribs) (Add visual for the redesigned research publications page)
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Riedel-research-mitra-reconfigurable-low-latency-and-power-efficient-in-memory-stochasti-0ccb97f9.jpg ‎(554 × 538 pixels, file size: 46 KB, MIME type: image/jpeg)

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Related architecture visual from Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures. Used as a temporary visual because the MITRA proceedings PDF is not yet publicly available. Marc Riedel is an author of both papers.

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current23:55, 18 August 2026Thumbnail for version as of 23:55, 18 August 2026554 × 538 (46 KB)MarcRiedel (talk | contribs)Add visual for the redesigned research publications page

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